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Subject:		HSM Translation into Synthesizable HDL?
Name:		Jeff Jones
Date Posted:		Jul 22, 08 - 9:38 AM
Email:		jeff.c.jones@baesystems.com
Message:		Is anyone familiar with methods to translate HSMs into a synthesizable Hardware Description Language (either VHDL or Verilog) targeted for FPGAs? I’m interested in either manual methods or tool based methods. Thanks for the inputs.

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